Single Cycle Processor

Single Cycle Processor

Single-cycle processors are composed of two main elements, namely the datapath and control. Within an instruction datapath, single cycle processors use one cycle. Each datapath contains the functional components of the processor that store data such as the program counter, the registers file, the instruction memory, elements that manipulate data such as the arithmetic and logic unit, adders, and the buses that transfer data between the various components (ANON, 2020). Control is the other component besides the datapath that commands the datapath on how to route and manipulate the data. The cycle consists of 32 bit composed of 32 single precisions or 16 double precisions.

The data held here are grouped in 8bit, 16bit, and 32bit for half word, integer values, and single-precision parity flags, respectively, with 64bit word for double-precision parity flags (Dennis et al., 2017). Instruction sets are stored through indexed and immediate branch addressing modes. The instruction memory is a state element that offers read access to program instructions giving addresses as input when giving corresponding instructions at those addresses. The execution of instructions involves fetching, decoding, fetching relevant address register, and forwarding it to the ALU before retrieving the next instruction address. The performance of this kind of processor is regulated by the instruction count, clock cycles, and cycle time.

The single processor’s design has the advantage of handling one clock cycle per instruction; hence it is dependable, but it has the limitation of taking long to execute because it is dependent on its speed is dependent on its slowest instruction. State elements constitute the functional hardware of the processor. The fetch execution cycle entails instruction fetching, Decoding, and its execution. When fetching a current instruction from the instruction memory, and address of the PC is used, Decoding determines the field within the instruction and execution performs the called operation. Upon completion of this cycle, the PC is updated, ready for the next instruction.

References

Batten, D., D’arcy, P. G., Glossner, C. J., Jinturkar, S., & Thilo, J. (2001). U.S. Patent No. 6,317,821. Washington, DC: U.S. Patent and Trademark Office.

Cs.fsu.edu. (2020). Retrieved 28 June 2020, from http://www.cs.fsu.edu/~zwang/files/cda3101/Fall2017/Lecture5_cda3101.pdf.

Dennis, Don Kurian, et al. ‘Single Cycle RISC-V Micro Architecture Processor and Its FPGA Prototype.’ 2017 7th International Symposium on Embedded Computing and System Design (ISED), IEEE, 2017, pp. 1–5. DOI.org (Crossref), doi:10.1109/ISED.2017.8303926.